module clkgen ( input wire clk, input wire reset_l, output reg clk_out ); parameter clk_counter_value = 4'b0100; reg [3:0] clk_counter;
always @(posedge clk or negedge reset_l) begin
if(!reset_l) begin
clk_counter <= 4'b0000;
end else if(clk_counter == clk_counter_value)begin
clk_counter <= 4'b0000;
end else begin
clk_counter <= clk_counter + 1;
end
end
always @(posedge clk or negedge reset_l) begin
if(!reset_l) begin
clk_out <= 4'b0000;
end else if(clk_counter == clk_counter_value) begin
clk_out <= ~clk_out;
end
end
endmodule
module clkgen_sim ();
//
reg reset_l_sig;
reg clk_sig;
//
clkgen clkgen(clk_sig,reset_l_sig,clk_out_sig);
//
initial begin
reset_l_sig <= 0;
#200
reset_l_sig <= 1;
#10000
$stop;
end
//
always begin
clk_sig <= 0;
#50;
clk_sig <= 1;
#50;
end
endmodule
vlog clkgen.v vlog clkgen_sim.v
vsim work.clkgen_sim
log -r *
add wave -position end sim:/clkgen_sim/clkgen/clk add wave -position end sim:/clkgen_sim/clkgen/clk_counter add wave -position end sim:/clkgen_sim/clkgen/clk_counter_value add wave -position end sim:/clkgen_sim/clkgen/clk_out add wave -position end sim:/clkgen_sim/clkgen/reset_l
run -all